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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST72F521M Fiches technique(PDF) 30 Page - STMicroelectronics |
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ST72F521M Fiches technique(HTML) 30 Page - STMicroelectronics |
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30 / 199 page  ST72521M/R/AR 30/199 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2.2 Monitoring a Voltage on the EVD pin This mode is selected by setting the AVDS bit in the SICSR register. The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set. This in- terrupt is generated on the rising and falling edges of the comparator output. This means it is generat- ed when either one of these two events occur: –VEVD rises up to VIT+(EVD) –VEVD falls down to VIT-(EVD) The EVD function is illustrated in Figure 16. For more details, refer to the Electrical Character- istics section. Figure 16. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1) VEVD VIT+(EVD) VIT-(EVD) AVDF 0 0 1 IF AVDIE = 1 Vhyst AVD INTERRUPT REQUEST INTERRUPT PROCESS INTERRUPT PROCESS |
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