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LTC2312-12

231212fa

For more information www.linear.com/LTC2312-12

applicaTions inForMaTion

Intermodulation Distortion (IMD)

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

If two pure sine waves of frequencies fa and fb are ap-

plied to the ADC input, nonlinearities in the ADC transfer

function can create distortion products at the sum and

difference frequencies m • fa ± n • fb, where m and n = 0,

1, 2, 3, etc. For example, the 2nd order IMD terms include

(fa±fb).Ifthetwoinputsinewavesareequalinmagnitude,

the value (in decibels) of the 2nd order IMD products can

be expressed by the following formula:

IMD(fa ± fb) = 20 • log[VA (fa ± fb)/VA (fa)]

TheLTC2312-12hasexcellentIMD,asshowninFigure15.

Figure 15. LTC2312-12 IMD Plot

231212 F15

INPUT FREQUENCY (kHz)

250

100

150

200

–20

fa fb

2fa – fb 2fb – fa

fb – fa

–40

–60

–80

–100

–120

–140

–160

VDD = 5V

fs = 500ksps

fa = 53.14kHz

fb = 58.142kHz

IMD2 (fb – fa) = –80dBc

IMD3 (2fb – fa) = –92dBc

fb + fa

Full-Power and –3dB Input Linear Bandwidth

The full-power bandwidth is the input frequency at which

theamplitudeofthereconstructedfundamentalisreduced

by 3dB for a full-scale input signal.

The –3dB linear bandwidth is the input frequency at which

the SINAD has dropped to 68dB (11 effective bits). The

LTC2312-12 has been designed to optimize the input

bandwidth,allowingtheADCtounder-sampleinputsignals

with frequencies above the converter’s Nyquist frequency.

The noise floor stays very low at high frequencies and

SINAD becomes dominated by distortion at frequencies

beyond Nyquist.

Recommended Layout

To obtain the best performance from the LTC2312-12 a

printed circuit board is required. Layout for the printed

circuit board (PCB) should ensure the digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital clocks or

signals alongside analog signals or underneath the ADC.

Figure 16 through Figure 20 are an example of a recom-

mended PCB layout. A single solid ground plane is used.

Bypass capacitors to the supplies are placed as close as

possible to the supply pins. Low impedance common

returns for these bypass capacitors are essential to the

low noise operation of the ADC. The analog input traces

are screened by ground. For more details and information

refer to DC1563, the evaluation kit for the LTC2312-12.

Bypassing Considerations

High quality tantalum and ceramic bypass capacitors

shouldbeusedattheVDD,OVDDandREFpins.Foroptimum

performance, a 2.2µF ceramic chip capacitor should be

usedfortheVDDandOVDDpins.Therecommendedbypass-

ing for the REF pin is also a low ESR, 2.2µF ceramic chip

capacitor. The traces connecting the pins and the bypass

capacitors must be kept as short as possible and should

be made as wide as possible avoiding the use of vias.

All analog circuitry grounds should be terminated at the

LTC2312-12. The ground return from the LTC2312-12 to

the power supply should be low impedance for noise free

operation. Digital circuitry grounds must be connected to

the digital supply common.

Spurious Free Dynamic Range (SFDR)

The spurious free dynamic range is the largest spectral

component excluding DC and the input signal. This value

is expressed in decibels relative to the RMS value of a

full-scale input signal.

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