MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER

MP8867 Rev.1.01

www.MonolithicPower.com

7

2/21/2017

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Parameter

Symbol Condition

Cb = 100pF

Cb = 400pF

Units

Min

Max

Min

Max

SCLH

and

SCL

clock

frequency

0

3.4

0

0.4

MHz

Set-up time for a repeated

start condition

160

-

600

-

ns

Hold time for a repeated start

condition

160

-

600

-

ns

Low period of the SCL clock

160

-

1300

-

ns

High period of the SCL clock

60

-

600

-

ns

Data set-up time

10

-

100

-

ns

Data hold time

0

70

0

-

ns

Rise time of SCLH signal

10

40

20*0.1Cb

300

ns

Rise time of SCLH signal after

a repeated start condition and

after an acknowledge bit

10

80

20*0.1Cb

300

ns

Fall time of SCLH signal

10

40

20*0.1Cb

300

ns

Rise time of SDAH signal

10

80

20*0.1Cb

300

ns

Fall time of SDAH signal

10

80

20*0.1Cb

300

ns

Set-up time for stop condition

160

-

600

-

ns

Bus free time between a stop

and start condition

160

-

1300

-

ns

Data valid time

-

16

-

90

ns

Data valid acknowledge time

-

160

-

900

ns

Capacitive load for each bus

line

SDAH and SCLH line

-

100

-

400

pF

SDAH + SDA line

and SCLH + SCL line

-

400

-

400

pF

Noise margin at the low level

For each connected

device

-

-

V

Noise margin at the high level

For each connected

device

-

-

V

NOTE: