PC755 datasheet(5/50 Pages) ATMEL

5 / 50 page

PC755/745

2138D–HIREL–06/03

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Supports flow through (register-buffer) synchronous burst SRAMs, pipelined

(register-register) synchronous burst SRAMs (3-1-1-1 or strobeless 4-1-1-1)

and pipelined (register-register) late-write synchronous burst SRAMs

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L2 configurable to direct mapped SRAM interface or split cache/direct

mapped or private memory

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Core-to-L2 frequency divisors of 1, 1.5, 2, 2.5, and 3 supported

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64-bit data bus

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Selectable interface voltages of 2.5V and 3.3V

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Parity checking on both L2 address and data

•

Memory Management Unit

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128 entry, 2-way set associative instruction TLB

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128 entry, 2-way set associative data TLB

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Hardware reload for TLBs

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Hardware or optional software tablewalk support

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8 instruction BATs and 8 data BATs

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8 SPRGs, for assistance with software tablewalks

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Virtual memory support for up to 4 hexabytes (2

52) of virtual memory

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Real memory support for up to 4 gigabytes (2

32) of physical memory

•

Bus Interface

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Compatible with 60X processor interface

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32-bit address bus

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64-bit data bus, 32-bit mode selectable

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Bus-to-core frequency multipliers of 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x,

7x, 7.5x, 8x, 10x supported

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Selectable interface voltages of 2.5V and 3.3V.

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Parity checking on both address and data busses

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Power Management

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Low-power design with thermal requirements very similar to PC740/750.

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Selectable interface voltage of 1.8V/2.0V can reduce power in output buffers

(compared to 3.3V)

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Three static power saving modes: doze, nap, and sleep

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Dynamic power management

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Testability

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LSSD scan design

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IEEE 1149.1 JTAG interface

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Integrated Thermal Management Assist Unit

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One-ship thermal sensor and control logic

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Thermal

Management

Interrupt

for

software

regulation

junction

temperature

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