PC755 datasheet(32/50 Pages) ATMEL

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PC755/745

2138D–HIREL–06/03

IEEE 1149.1 AC Timing

Specifications

Timing Specifications

Table 17 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure

18, Figure 19, Figure 20, and Figure 21.

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in ques-

tion. The output timings are measured at the pins. All output timings assume a purely resistive 50

Ω load (See Figure 18).

Time

-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non

-JTAG signal input timing with respect to TCK.

4. Non

-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the PC755.

Figure 18. ALTERNATE AC Test Load for the JTAG Interface

Table 17. JTAG AC Timing Specifications (Independent of SYSCLK)(1)

Parameter

Symbol

Min

Max

Unit

TCK Frequency of operation

fTCLK

MHz

TCK Cycle time

fTCLK

62.5

TCK Clock pulse width measured at 1.4V

JHJL

TCK Rise and fall times

tJR & tJF

TRST Assert time(2)

tTRST

Input Setup Times:(3)

Boundary

-scan data

TMS, TDI

tDVJH

tIVJH

Input Hold Times:(3)

Boundary

-scan data

TMS, TDI

tDXJH

IXJH

Valid Times:(4)

Boundary

-scan data

TDO

JLDV

tJLOV

Output Hold Times:(4)

Boundary

-scan data

TDO

JLDV

tJLOV

TCK to output high impedance:(4)(5)

Boundary

-scan data

TDO

tJLDZ

JLOZ

OVDD/2

OUTPUT

Z0 = 50Ω

RL = 50Ω

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