LAN9220 datasheet(39/142 Pages) MICROCHIP

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DS00002417A-page 39

LAN9220

3.11

Detailed Reset Description

The LAN9220 has four reset sources:

• Hardware Reset Input Pin (nRESET)

• Soft Reset (SRST)

• PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)

• PHY Soft Reset via PHY Basic Control Register (PHY REG 0.15)

Table 3-11 shows the effect of the various reset sources on the LAN9220's circuitry.

Note 3-11

After any PHY reset, the application should wait until the "Link Status" bit in the PHY's "Basic Status

FIFO will only be sent when the Link Status returns to "Up".

Note 3-12

After a power-up, nRESET or SRST, the LAN9220 will automatically check for the presence of an

external EEPROM. After any of these resets the application must verify that the EPC Busy Bit

(E2P_CMD, bit 31) is cleared before attempting to access the EEPROM, or change the function of

the GPO/GPIO signals, or before modifying the ADDRH or ADDRL registers in the MAC.

Note 3-13

HBI - “Host Bus Interface”, NASR - Not affected by software reset.

APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) after an internal

reset (22ms). If the software driver polls this bit and it is not set within 100ms, then an error

condition occurred.

3.11.1

HARDWARE RESET INPUT (NRESET)

A hardware reset will occur when the nRESET input signal is driven low. The READY bit in the PMT_CTRL register can

be read from the host interface, and will read back a ‘0’ until the hardware reset is complete. Upon completion of the

hardware reset, the READY bit in PMT_CTRL is set high.

After the “READY” bit is set, the LAN9220 can be configured via its control registers. The nRESET signal is pulled-high

internally by the LAN9220 and can be left unconnected if unused. If used, nRESET must be driven low for a minimum

period as defined in Section 6.10, "Reset Timing," on page 124. If nRESET is unused, the device must be reset following

power-up via a soft reset (SRST).

APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately. If

the software driver polls this bit and it is not set within 100ms, then an error condition

occurred.

Note:

For proper operation, the LAN9220 must be reset on power-up via the hardware reset input (nRESET) or

soft reset (SRST). To accomplish this, nRESET should be asserted for the minimum period of 30ms at

power-up. Alternatively, a soft reset may be performed following power-up by setting the SRST bit of the

HW_CFG register once the READY bit in the PMT_CTRL register has been set. Refer to Section 3.11.1,

"Hardware Reset Input (nRESET)" and Section 3.11.3, "Soft Reset (SRST)" for additional information.

TABLE 3-11:

RESET SOURCES AND AFFECTED CIRCUITRY

Reset Source

PLL

HBI

Note

NASR

Registers

Note 3-13

MIL

MAC

PHY

Note 3-11

EEPROM MAC

ADDR. Reload

Note 3-12

Config.

Straps

Latched

nRESET

SRST

PHY_RST

PHY REG 0.15

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