Features
■ 2, 3 or 4 output buffered clock distribution
■ Single-ended square wave (or sine wave) clock input
■ Rail-to-rail (0 V to VTCXO) square wave output
■ Individual enable pin for each output
■ 1.8 V, high PSRR LDO for external clock source voltage supply (VTCXO)
■ No AC coupling capacitor needed
■ Ultra-low phase noise and standby current
■ Common system clock request, open drain, active low
■ Clock enable signal polarities factory programmable (STCD23x0)
■ Option pins allow clock enable polarities to be user configurable (STCD22x0 and STCD24x0)
■ High isolation output-to-output & output-to-input
■ 2.5 V to 5.1 V battery supply voltage
■ 40 pF max load driving capability per output
■ Available in chip scale package (CSP)
■ Operating temperature : –20 °C to 85 °C

Applications
■ Multimode RF clock reference
■ Baseband peripheral device clock reference
■ Mobile Internet Devices (MIDs) Flip Chip (12-bump, 16-bump)