Features
• Single 2.3 V - 3.6 V or 2.5 V - 3.6 V supply
• Serial Peripheral Interface (SPI) compatible
• Supports SPI modes 0 and 3
• Supports RapidS™ operation
• Continuous read capability through entire array
• Up to 85 MHz
• Low-power read option up to 15 MHz
• Clock-to-output time (tV) of 6 ns maximum
• User-configurable page size
• 512 bytes per page
• 528 bytes per page (default)
• Page size can be factory pre-configured for 512 bytes
• Two fully independent SRAM data buffers (512/528 bytes)
• Allows receiving data while reprogramming the main memory array
• Flexible programming options
• Byte/Page Program (1 to 512/528 bytes) directly into main memory
• Buffer Write
• Buffer to Main Memory Page Program
• Flexible erase options
• Page Erase (512/528 bytes)
• Block Erase (4 kB)
• Sector Erase (128 kB)
• Chip Erase (16 Mbits)
• Program and Erase Suspend/Resume
• Advanced hardware and software data protection features
• Individual sector protection
• Individual sector lockdown to make any sector permanently read-only
• 128-byte, One-Time Programmable (OTP) Security Register
• 64 bytes factory programmed with a unique identifier
• 64 bytes user programmable
• Hardware and software controlled reset options
• JEDEC Standard Manufacturer and Device ID Read
• Low-power dissipation
• 400 nA Ultra-Deep Power-Down current (typical)
• 5 µA Deep Power-Down current (typical)
• 25 µA Standby current (typical)
• 7 mA Active Read current (typical @ 15 MHz))
• Endurance: 100,000 program/erase cycles per page minimum
• Data retention: 20 years
• Complies with full industrial temperature range
• Green (Pb/Halide-free/RoHS compliant) packaging options
• 8-lead SOIC (0.150" wide and 0.208" wide)
• 8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
• 11-ball Wafer Level Chip Scale Package
• Die in Wafer Form (contact factory for availability)

1. Description
The AT45DB161E is a 2.3 V or 2.5 V minimum, serial-interface sequential access Flash memory ideally suited for
a wide variety of digital voice, image, program code, and data storage applications. The AT45DB161E also
supports the RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of
memory are organized as 4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the
AT45DB161E also contains two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a
page in the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a
system's ability to write a continuous data stream. Also, the SRAM buffers can be used as additional system
scratch pad memory, and E2PROM emulation (bit or byte alterability) can be easily handled with a self-contained
three step read-modify-write operation.
Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel
interface, this device uses a serial interface to sequentially access its data. The simple sequential access
dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes
switching noise, and reduces package size. The device is optimized for use in many commercial and industrial
applications where high-density, low-pin count, low-voltage, and low-power are essential.
To allow for simple in-system re-programmability, the AT45DB161E does not require high input voltages for
programming. The device operates from a single 2.3 V to 3.6 V or 2.5 V to 3.6 V power supply for the erase and
program and read operations. The AT45DB161E is enabled through the Chip Select pin (CS) and accessed via a
Three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.