NB4L16MMNEVB Fiches technique, PDF

Fabricant	No de pièce	Fiches technique	Description
ON Semiconductor	NB4L16MMNG	919Kb/12P	2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator with Internal Termination February, 2006 ??Rev. 1
	NB4L16MMNR2	919Kb/12P	2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator with Internal Termination February, 2006 ??Rev. 1
	NB4L16MMNR2G	919Kb/12P	2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator with Internal Termination February, 2006 ??Rev. 1
	NB4L16MMN	919Kb/12P	2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator with Internal Termination February, 2006 ??Rev. 1
	NB4L16M	919Kb/12P	2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator with Internal Termination February, 2006 ??Rev. 1
	NB4L339	117Kb/7P	3.3V 1:4 Clock Fanout Buffer September, 2006 ??Rev. 0
	NB4L339	144Kb/12P	2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator September, 2012 ??Rev. 3
	NB4L339MNG	176Kb/12P	2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan?뭀ut Buffer January, 2007 ??Rev. P2
	NB4L339MNG	144Kb/12P	2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator September, 2012 ??Rev. 3
	NB4L339MNR2G	176Kb/12P	2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan?뭀ut Buffer January, 2007 ??Rev. P2
	NB4L339MNR4G	144Kb/12P	2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator September, 2012 ??Rev. 3
	NB4L339	176Kb/12P	2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan?뭀ut Buffer January, 2007 ??Rev. P2
	NB4L339	144Kb/12P	2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator September, 2012 ??Rev. 3
	NB4L52	135Kb/8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination January, 2007 ??Rev. 2
	NB4L52	149Kb/8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop August, 2009 ??Rev. 3
	NB4L52MNG	135Kb/8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination January, 2007 ??Rev. 2
	NB4L52MNG	149Kb/8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop August, 2009 ??Rev. 3
	NB4L52MNR2G	135Kb/8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination January, 2007 ??Rev. 2
	NB4L52MNR2G	149Kb/8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop August, 2009 ??Rev. 3
	NB4L52	135Kb/8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination January, 2007 ??Rev. 2

NB4L16MMNEVB Fiches technique, PDF

NB4L16MMNEVB Datasheet ,PDF

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