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ST72F324J Fiches technique(PDF) 45 Page - STMicroelectronics

No de pièce ST72F324J
Description  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
PDF  156 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F324J Fiches technique(HTML) 45 Page - STMicroelectronics

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I/O PORTS (Cont’d)
Figure 30. I/O Port General Block Diagram
Table 10. I/O Port Mode Options
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to VDD is not implemented in the
true open drain pads. A local protection between
the pad and VSS is implemented to protect the de-
vice against positive stress.
Configuration Mode
Pull-Up
P-Buffer
Diodes
to VDD
to VSS
Input
Floating with/without Interrupt
Off
Off
On
On
Pull-up with/without Interrupt
On
Output
Push-pull
Off
On
Open Drain (logic level)
Off
True Open Drain
NI
NI
NI (see note)
DR
DDR
OR
PAD
VDD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
1
0
OR SEL
DDR SEL
DR SEL
PULL-UP
CONDITION
P-BUFFER
(see table below)
N-BUFFER
PULL-UP
(see table below)
1
0
ANALOG
INPUT
If implemented
ALTERNATE
INPUT
VDD
DIODES
(see table below)
EXTERNAL
SOURCE (eix)
INTERRUPT
CMOS
SCHMITT
TRIGGER
REGISTER
ACCESS



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