CAT24FC16 datasheet(3/11 Pages) CATALYST

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CAT24FC16

Doc No. 1054, Rev. G

Write Cycle Limits

Symbol

Parameter

MinTyp

Max

its

tWR

Write Cycle Time

A.C. CHARACTERISTICS

VCC = 1.8 V to 5.5 V, unless otherwise specified.

Read & Write Cycle Limits

Symbol

Parameter

1.8 V - 5.5 V

2.5 V - 5.5 V

MinMax

Min Max

its

FSCL

Clock Frequency

100

400

kHz

TI(1)

Noise Suppression Time

100

Constant at SCL, SDA Inputs

tAA

SCL Low to SDA Data Out

3.5

0.9

µs

and ACK Out

tBUF(1)

Time the Bus Must be Free Before

4.7

1.3

µs

a New Transmission Can Start

tHD:STA

Start Condition Hold Time

0.6

µs

tLOW

Clock Low Period

4.7

1.3

µs

tHIGH

Clock High Period

0.6

µs

tSU:STA

Start Condition Setup Time

4.7

0.6

µs

(for a Repeated Start Condition)

tHD:DAT

Data In Hold Time

tSU:DAT

Data In Setup Time

250

100

tR(1)

SDA and SCL Rise Time

0.3

µs

tF(1)

SDA and SCL Fall Time

300

tSU:STO

Stop Condition Setup Time

0.6

µs

tDH

Data Out Hold Time

100

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Power-Up Timing(1)(2)

Symbol

Parameter

MinTyp

Max

its

tPUR

Power-up to Read Operation

tPUW

Power-up to Write Operation

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to remain

high, and the device does not respond to its slave

address.

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