MP3276AP datasheet(7/16 Pages) EXAR

7 / 16 page

MP3276

Rev. 4.00

The MP3276 is easily interfaced to a wide variety of micropro-

cessors and other digital systems. Discussion of the timing re-

quirements of the MP3276 control signals follows.

Figure 1. shows a complete timing diagram for the MP3276

convert start operation.

Either WR or CS may be used to initiate a conversion. We

recommend using WR as used in

Figure 1. It is quieter and has

less propagation delay than CS. If CS is used to trigger the con-

version the specified set-up times will be longer.

A conversion is started by taking WR low, then high again

(conversion is enabled on the rising edge of WR). There are two

possible conditions that will affect conversion timing.

1. ADEN = 1. At the falling edge of WR, the input channel is

determined by the data present on the address bits. The

track and hold begins to settle after which STL returns low,

indicating that the multiplexer and the buffer amp have set-

tled to less than 1/2 LSB of final value. If the rising edge of

WR returns high prior to STL going low, conversion will begin

on the falling edge of STL. If the rising edge of WR is delayed

until after STL returns low, the input signal is sampled and

the conversion is started at the rising edge of WR giving the

user better control of the sampling time.

2. ADEN = 0. At the falling edge of WR the data present at the

address is ignored and the channel selected during the pre-

vious conversion remains selected. In this case the track

and hold settling time is omitted and STL never goes high. At

the rising edge of WR the input signal is sampled, and con-

version is started.

There are two possible states that the data outputs could be in

during a conversion.

1. If RD is held high during a conversion the outputs would re-

main high impedance throughout the conversion. This is the

preferred method of operation as any noise present on the

data bus is rejected.

2. If RD and CS are held low during a conversion, the data pre-

sent will be from the previous conversion until the present

conversion is completed when STS returns low. The data

from the new conversion will appear on the outputs. The

state of RD or CS should not change during a conversion.

Once a conversion is started and the STL or STS line goes

high, convert start commands will be ignored until the conver-

sion cycle is completed. The output data buffers cannot be en-

abled during conversion. In addition, all inputs and outputs

which change during conversion can introduce noise, and

should be avoided when possible.

ADC Control Timing

Table 2. ADC Write Timing

(See Figure 1.)

°C

Tmin to

Tmax

Limits

Comments/Test Conditions

CS to WR Set-Up Time

ns min

CS to WR Hold Time

ns min

Address to WR Set-Up Time

ns min

Address to WR Hold Time

ns min

WR Pulse Width

ns min

ADEN to WR Set-Up Time

ns min

ADC Conversion Timing

WR to STL Delay

150

ns max

Load ckt of Figure 5, CL = 20 pF,

ADEN = 1

STL High (mux/amp settle)

µs max

Load ckt of Figure 5, CL = 20 pF

STL to STS Low (Converting)

µs max

Load ckt of Figure 5, CL = 20 pF

WR to STS High (ADEN = 0)

t12

200

250

ns max

STL = 0 when ADEN = 0

WR to STS Low (ADEN = 1)

t10

µs max

STS High to Bus Relinquish Time

t13

150

ns max

Load ckt of Figure 4

STS Low to Data Valid (RD = 0)

t14

ns max

Load ckt of Figure 3, CL = 20 pF

ADC Write Timing

Time

Interval

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