PI6CU877 datasheet(3/11 Pages) PERICOM

3 / 11 page

PS8689B

08/05/04

PI6CU877

PLL Clock Driver for

1.8V DDR2 Memory

Pinout Table

Pin Name

Characteristics

Desctription

AGND

Ground

Analog ground

AVDD

1.8V nominal

Analog power

Differential Input

Clock input with a (10K - 100KΩ) pulldown resistor

Differential Input

Complementary clock input with a (10K - 100KΩ) pulldown resistor

FBIN

Differential Input

Complementary feedback clock input

FBIN

Differential Input

Feedback clock input

FBOUT

Differenital Output

Complementary Feedback clock output

FBOUT

Differential Output

Feedback clock output

LVCMOS input

Output enable (async.)

LVCMOS input

Output select (tied to GND or VDDQ)

GND

Ground

VDDQ

1.8V nominal

Logic and output power

Y[0:9]

Differential Outputs

Clock outputs

Y[0:9]

Differential Outputs

Complementary clock outputs

No Ball (VFBGA only)

Function Table

Inputs

Outputs

PLL State

AVDD

FBOUT

GND

Bypass/Off

GND

Bypass/Off

GND

L(Z)(1)

Bypass/Off

GND

L(Z)(1),

Y7 active

L(Z)(1),

Y7 active

Bypass/Off

1.8V (nom)

L(Z)(1)

1.8V (nom)

L(Z)(1),

Y7 active

L(Z)(1),

Y7 active

1.8V (nom)

L(Z)(1)

Off

1.8V (nom)

Reserved

Notes:

L(Z) means the outputs are disabled to a low state meeting the IODL limit on DC Specification

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