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AT975 Fiches technique(PDF) 1 Page - Power Semiconductors

No de pièce AT975
Description  PHASE CONTROL THYRISTOR
PDF  6 Pages
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Fabricant  POSEICO [Power Semiconductors]
Site Internet  http://www.poseico.com
Logo POSEICO - Power Semiconductors

AT975 Fiches technique(HTML) 1 Page - Power Semiconductors

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PHASE CONTROL THYRISTOR
AT975
Repetitive voltage up to
5200 V
Mean on-state current
3263 A
Surge current
60
kA
FINAL SPECIFICATION
Feb. 17 - Issue: 1
Symbol
Characteristic
Conditions
Tj
[°C]
Value
Unit
BLOCKING
V RRM
Repetitive peak reverse voltage
125
5200
V
V RSM
Non-repetitive peak reverse voltage
125
5300
V
V DRM
Repetitive peak off-state voltage
125
5200
V
I RRM
Repetitive peak reverse current
V=VRRM
125
300
mA
I DRM
Repetitive peak off-state current
V=VDRM
125
300
mA
CONDUCTING
I T (AV)
Mean on-state current
180° sin, 50 Hz, Th=55°C, double side cooled
3263
A
I T (AV)
Mean on-state current
180° sin, 50 Hz, Tc=85°C, double side cooled
2592
A
I TSM
Surge on-state current
sine wave, 10 ms
125
60,0
kA
I² t
I² t
without reverse voltage
18000 x1E3
A²s
V T
On-state voltage
On-state current =
7850 A
25
2,30
V
V T(TO)
Threshold voltage
125
1,07
V
r T
On-state slope resistance
125
0,190
mohm
SWITCHING
di/dt
Critical rate of rise of on-state current, min.
From 67% VDRM, gate 10V 5ohm
125
200
A/µs
dv/dt
Critical rate of rise of off-state voltage, min.
Linear ramp up to 67% of VDRM
125
1000
V/µs
td
Gate controlled delay time, typical
VD=100V, gate source 10V, 10 ohm , tr=5 µs
25
.
µs
tq
Circuit commutated turn-off time, typical
dv/dt = 20 V/µs linear up to 75% VDRM
400
µs
Q RR
Reverse recovery charge
di/dt=-20 A/µs, I= 2150 A
125 .
µC
I RR
Peak reverse recovery current
VR= 50 V
.
A
I H
Holding current, typical
VD=5V, gate open circuit
25
500
mA
I L
Latching current, typical
VD=12V, tp=50µs
25
1500
mA
GATE
V GT
Gate trigger voltage
VD=12V
25
2,5
V
I GT
Gate trigger current
VD=12V
25
250
mA
V GD
Non-trigger gate voltage, min.
VD=67%VDRM
125
0,25
V
V FGM
Peak gate voltage (forward)
10
V
I FGM
Peak gate current
10
A
V RGM
Peak gate voltage (reverse)
10
V
P GM
Peak gate power dissipation
Pulse width 100 µs
150
W
P G
Average gate power dissipation
3
W
MOUNTING
R th(j-c)
Thermal impedance, DC
Junction to case, double side cooled
6,0
°C/kW
R th(c-h)
Thermal impedance
Case to heatsink, double side cooled
1,5
°C/kW
T j
Operating junction temperature
-30 / 125
°C
F
Mounting force
80.0 / 100.0
kN
Mass
3000
g
ORDERING INFORMATION : AT975 S 52
standard specification
VDRM&VRRM/100
POSEICO SPA
Via Pillea 42-44, 16153 Genova - ITALY
Tel. + 39 010 8599400 - Fax + 39 010 8682006
Sales Office:
Tel. + 39 010 8599400 - sales@poseico.com
Page 1 of 6


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