WM8782SEDSSLASHR datasheet(8/19 Pages) WOLFSON

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WM8782

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PP, May 2004, Rev 1.0

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Figure 1 System Clock Timing Requirements

Test Conditions

DVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode, fs = 48kHz, Slave Mode, MCLK = 256fs, 24-bit data, unless otherwise

stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

TMCLKL

MCLK System clock pulse width low

TMCLKH

MCLK System clock cycle time

TMCLKY

MCLK duty cycle

TMCLKDS

40:60

60:40

Table 1 Master Clock Timing Requirements

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

DVDD = 3.3V, DGND = 0V, TA = +25

oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge

tDL

DOUT propagation delay from BCLK falling edge

tDDA

Table 2 Digital Audio Data Timing - Master Mode

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