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PC33879EK/R2 Fiches technique(PDF) 10 Page - Motorola, Inc |
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PC33879EK/R2 Fiches technique(HTML) 10 Page - Motorola, Inc |
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10 / 20 page ![]() 33879 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 10 Timing Diagrams Figure 2. SPI Timing Diagram Figure 3. Valid Data Delay Time and Valid Time Test Circuit Figure 4. Valid Data Delay Time and Valid Time Waveforms Figure 5. Enable and Disable Time Waveforms tDO(dis) 0.7 VDD 0.2 VDD 0.2 VDD 0.7 VDD 0.2 VDD tlead tDO(en) tDI(su) tDI(hold) tvalid tlag CS SCLK DI DO MSB in MSB out LSB out 0.7 VDD 0.2 VDD DO CL = 200 pF VDD = 5.0 V SCLK 33879 Under Test NOTE: CL represents the total capacitance of the test fixture and probe. (Low-to-High) tf(DI) tr(DI) 0.2 VDD 0.7 VDD 0.2 VDD 0.7 VDD tvalid tr(DO) VOL VOH VOL VOH 0.2 VDD 0.7 VDD 0 V 3.3/5.0 V < 50 ns 50% < 50 ns DO SCLK (High-to-Low) DO 90% tf(CS) tr(CS) VOH VOL 0 V 3.3/5.0 V DO tDO(dis) tDO(en) tDO(dis) tDO(en) (Tri-State to Low) 0.7 VDD 0.2 VDD <50 ns <50 ns CS 90% DO (Tri-State to High) 10% 10% 90% 10% VTri-State VTri-State Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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