CDCU877AGQL datasheet(3/17 Pages) TI

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CDCU877/CDCU877A

1.8V PHASE LOCK LOOP CLOCK DRIVER

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 1. Terminal Functions

NAME

BGA

MLF

I/O

DESCRIPTION

AGND

Analog ground

AVDD

Analog power

Clock input with a (10 k

Ω to 100 kΩ) pulldown resistor

Complementary clock input with a (10 k

Ω to 100 kΩ) pulldown resistor

FBIN

Feedback clock input

FBIN

Complementary feedback clock input

FBOUT

Feedback clock output

FBOUT

Complementary feedback clock output

Output enable (asynchronous)

Output select (tied to GND or VDD)

GND

B2, B3, B4, B5,

C2, C5, H2, H5,

J2, J3, J4, J5

Ground

VDDQ

D2, D3, D4, E2,

E5, F2, G2, G3,

G4, G5

1, 6, 9, 15, 20,

23, 28, 31, 36

Logic and output power

Y[0:9]

A2, A1, D1, J1,

K3, A5, A6, D6,

J6, K4

38, 39, 3, 11, 14,

34, 33, 29, 19, 16

Clock outputs

Y[0:9]

A3, B1, C1, K1,

K2, A4, B6, C6,

K6, K5

37, 40, 2, 12, 13,

35, 32, 30, 18, 17

Complementary clock outputs

Table 2. Function Table

INPUTS

OUTPUTS

PLL

AVDD

FBOUT

PLL

GND

Bypassed/

Off

GND

Bypassed/

Off

GND

Bypassed/

Off

GND

Y7 Active

Bypassed/

Off

1.8 V Nominal

Y7 Active

1.8 V Nominal

Off

Reserved

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