8-3

Functional Diagram

TRUTH TABLE

INPUTS

DATA I/O

OPERATION OR FUNCTION

OEAB OEBA

CAB

CBA

SAB

SBA

A0 THRU A7

B0 THRU B7

CD74FCT653

CD74FCT654

L

L

H

H

H or L

↑

H or L

↑

X

X

X

X

Input

Input

Input

Input

Isolation (Note 1)

Store A and B Data

Isolation (Note 1)

Store A and B Data

X

H

H

H

↑

↑

H or L

↑

X

X (3)

X

X

Input

Input

Unspecified (2)

Output

Store A, Hold B

Store A in both registers

Store A, Hold B

Store A in both registers

L

L

X

L

H or L

↑

↑

↑

X

X

X

X (3)

Unspecified (2)

Output

Input

Input

Hold A, Store B

Store B in both registers

Hold A, Store B

Store B in both registers

L

L

L

L

X

X

X

H or L

X

X

L

H

Output

Output

Input

Input

Real-Time B Data to A Bus

Stored B Data to A Bus

Real-Time B Data to A Bus

Stored B Data to A Bus

H

H

H

H

X

H or L

X

X

L

H

X

X

Input

Input

Output

Output

Real-Time A Data to B Bus

Stored A Data to B Bus

Real-Time A Data to B Bus

Stored A Data to B Bus

H

L

H or L H or L

H

H

Output

Output

Stored A Data to B Bus

Stored B Data to A Bus

Stored A Data to B Bus

Stored B Data to A Bus

NOTES:

1. To prevent excess currents in the High-Z (isolation) modes, all I/O terminals should be terminated with 10k

Ω to 1MΩ resistors.

2. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always

enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.

3. Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered in order to load both registers.

4

5

6

7

8

9

10

11

20

19

18

17

16

15

14

13

B0

B1

B2

B3

B4

B5

B6

B7

A0

A1

A2

A3

A4

A5

A6

A7

B DATA PORT

A DATA PORT

OEBA

OEAB

CAB CLOCK

CBA CLOCK

21

3

1

23

2

22

SAB SOURCE

SBA SOURCE

DATA SOURCE

SELECTION

INPUTS

FLIP-FLOP

CLOCKS

GND = PIN 12

CD74FCT653, CD74FCT654