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AT83C5111 Fiches technique(PDF) 66 Page - ATMEL Corporation |
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AT83C5111 Fiches technique(HTML) 66 Page - ATMEL Corporation |
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66 / 86 page ![]() 66 AT8xC5111 4190A–8051–11/02 Table 7. IPH0 Register IPH0 - Interrrupt Priority High Register Reset value = X0X0 0000b Not bit addressable 765 43210 - PPCH - PSH PT1H PX1H PT0H PX0H Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6PPCH PCA Counter Interrupt Priority level most significant bit PPCH PPC Priority Level 0 0 Lowest 01 10 1 1 Highest 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4PSH Serial port Priority High bit PSH PS Priority Level 0 0 Lowest 01 10 1 1 Highest 3PT1H Timer 1 overflow interrupt Priority High bit PT1H PT1 Priority Level 0 0 Lowest 01 10 1 1 Highest 2PX1H External interrupt 1 Priority High bit PX1H PX1 Priority Level 0 0 Lowest 01 10 1 1 Highest 1PT0H Timer 0 overflow interrupt Priority High bit PT0H PT0 Priority Level 0 0 Lowest 01 10 1 1 Highest 0PX0H External interrupt 0 Priority High bit PX0H PT0 Priority Level 0 0 Lowest 01 10 1 1 Highest |
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