LAN91C100FD datasheet(45/68 Pages) SMSC

45 / 68 page

SMSC DS – LAN91C100FD REV. B

Page 45

Rev. 05/31/2000

2) One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1. TX EMPTY

INT is generated only after transmitting the last packet in the FIFO.

TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and

therefore the FIFO will not be emptied.

This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that when

AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed successfully.

Note: The pointer register is shared by any process accessing the LAN91C100FD memory. In order to allow

processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it,

saving it, and restoring it before returning from the interrupt.

Typically there would be three processes using the pointer:

1) Transmit loading (sometimes interrupt driven)

2) Receive unloading (interrupt driven)

3) Transmit Status reading (interrupt driven).

1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also

required from interrupt service routines.

FIGURE 11 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU

FIFO

TX COMPLETION

FIFO

CSMA/CD

LOGICAL

ADDRESS

PACKET #

MMU

PHYSICAL ADDRESS

RAM

CPU ADDRESS

CSMA ADDRESS

RX PACKET

NUMBER

RX FIFO

PACKET NUMBER

PACK # OUT

M.S. BIT ONLY

'EMPTY'

'NOT EMPTY'

TX DONE

PACKET NUMBER

'NOT EMPTY'

INTERRUPT

STATUS REGISTER

RCV

INT

TX EMPTY

INT

ALLOC

INT

TWO

OPTIONS

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