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ICS950812

0542G—08/21/03

Power Down De-Assertion Mode

The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping

of the power supply until the time that stable clocks are output from the clock chip. If the I

to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.

Test Configuration Diagrams

CPU 1.0V Configuration test load board termination

TLA

TLB

1%

MULTSEL Pin must be Low

Rs=33 Ohms

1%

Rs=33 Ohms

1%

Rp=63.4 Ohms

1%

Rp=63.4 Ohms

1%

Rdif=475 Ohms

1%

2pF

5%

2pF

5%

CPUCLKT test

point

CPUCLKC test

point

CLK408

CPU 0.7V Configuration test load board termination

TLA

TLB

MULTSEL Pin must be High

Rs=33 Ohms

5%

Rs=33 Ohms

5%

Rp=49.9 Ohms

1%

Rp=49.9 Ohms

1%

Rset=475 Ohms

1%

2pF

5%

2pF

5%

CPUCLKT test

point

CPUCLKC test

point

CLK408