STSAM9708 datasheet(5/30 Pages) ATMEL

5 / 30 page

ATSAM9708

1772D–DRMSD–01/04

Note:

1. Memory group pins are powered by V

CC2 power rail.

Note:

1. X2 cannot be used to drive external circuitry.

RAS

I/O

DRAM/SDRAM row address strobe. At the end of reset RAS is tested to

determine memory type configuration (pulled high to select SDRAM type). RAS

should be pulled to V

CC or GND through an external 10K resistor.

CAS

I/O

DRAM/SDRAM column address strobe. At the end of reset CAS is tested to

determine memory type configuration (pulled high to select DRAM type). CAS

should be pulled to V

CC or GND through an external 10K resistor.

REFRESH

I/O

Indicates that a DRAM/SDRAM memory refresh cycle is in progress. To be

used with multiple SIMM/DIMM modules to force refresh simultaneously on all

modules. At the end of reset REFRESH is tested to select bootstrap state

(pulled high to start built-in CPU bootstrap in case of ROMless applications).

Table 5. Miscellaneous Group

Name

Pin Count

Type

Function

LFT

ANA

PLL low pass filter. Should be connected to an external RC network.

TEST

Test pin. Should be returned to GND.

LDTEST

Test pin. Should be returned to GND.

PDWN

Power down, active low

RESET

Master reset input, active low. Schmidt trigger input.

X1, X2(1)

–

Crystal connection. Crystal frequency should be f

S x 256 (typ 11.2896 MHz).

Crystal frequency is internally multiplied by 4 to provide the IC master clock. X1

can also be used as external clock input (3.3V input).

Table 4. Memory Group(1) (Continued)

Name

Pin Count

Type

Function

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