PC87410VLK datasheet(9/16 Pages) NSC

9 / 16 page

Configuration Registers The configuration register map is shown in Table I (Continued)

TABLE I

(Continued)

Reg

Description

(in HEX)

IDE CHANNEL 0 FUNCTION REGISTER

bit3

channel 0 IO decode enable bit

1 enable (default)

0 disable

bit2

IORDY0 function control

1 enable

0 disable (default)

bit1

CH0

INT status (read only)

1 interrupt pending

0 no interrupt pending

bit0

CH0

INT request to be masked or not

1 be masked

0 not be masked (default)

IDE CHANNEL 1 TIMING CONTROL REGISTER

This register is the cycle control register for 170h port

Default is set at B5h (Note 1)

bit 7 6

addresschip select setup time

0 0

1 PCI clk

0 1

2 PCI clk

1 0

3 PCI clk

(default)

1 1

4 PCI clk

bit543

addresschip selectwrite data hold time

0 0 0

1 PCI clk

0 0 1

2 PCI clk

0 1 0

3 PCI clk

0 1 1

4 PCI clk

1 0 0

5 PCI clk

1 0 1

6 PCI clk

1 1 0

8 PCI clk

(default)

1 1 1

12 PCI clk

bit210

Command active time

0 0 0

2 PCI clk

0 0 1

3 PCI clk

0 1 0

4 PCI clk

0 1 1

5 PCI clk

1 0 0

6 PCI clk

1 0 1

8 PCI clk

(default)

1 1 0

12 PCI clk

1 1 1

16 PCI clk

IDE CHANNEL 1 READAHEAD COUNTER LOW BYTE

It provides values for loading bit0 – bit7 of read

ahead counter

bit0

bit0 of the read

ahead counter

bit1

bit1 of the read

ahead counter

bit2

bit2 of the read

ahead counter

bit3

bit3 of the read

ahead counter

bit4

bit4 of the read

ahead counter

bit5

bit5 of the read

ahead counter

bit6

bit6 of the read

ahead counter

bit7

bit7 of the read

ahead counter

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