| Moteur de recherche de fiches techniques de composants électroniques |
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PC87410 Fiches technique(PDF) 12 Page - National Semiconductor (TI) |
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PC87410 Fiches technique(HTML) 12 Page - National Semiconductor (TI) |
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12 / 16 page ![]() Timing Specification Symbol Parameter Conditions Min Max Units t0 CLK period 30 ns t1 PCI signals input setup time (Note) 7 ns t2 PCI signals CLK to output valid 6 12 ns t3 CLK to CHx DA 20 CHx CS1 3 6 15 ns CHx IOR CHx IOW IDE D 150 valid t4 IORDYx setup time to CLK rising 6 ns t5 IORDYx hold time from CLK rising 0 ns t6 CHx DA 20 CHx CS1 3 setup 1 4 CLK time to CHx IOR CHx IOW falling t7 CHx IOR CHx IOW active 2 16 CLK pulse width t8 CHx DA 20 CHx CS1 3 hold 1 12 CLK time from CHx IOR Chx IOW rising t9 IDE D 150 read data setup time 10 ns to CLK rising t10 IDE D 150 read data hold time 0ns from CLK rising t11 CLK to AD 310 read data valid delay 0 14 ns t12 CHx DA 20 CHx CS1 3 setup time to CHx IOR CHx IOW falling 4 4 CLK (Non Data Cycle) t13 CHx DA 20 CHx CS1 3 hold time from CHx IOR CHx IOW 5 6 CLK rising (Non Data Cycle) t14 CHx IOR CHx IOW active pulse 15 16 CLK width (Non Data Cycle) Note If fast decode is enabled the address setup time (t1 min) is 12 ns 12 |
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