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ST2329B Fiches technique(PDF) 15 Page - STMicroelectronics

No de pièce ST2329B
Description  2-bit dual supply level translator without direction control pin, open drain output
PDF  23 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST2329B Fiches technique(HTML) 15 Page - STMicroelectronics

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DocID023359 Rev 3
15/23
ST2329B
Electrical characteristics
Table 11. AC characteristics - test conditions: VL = 2.5 - 2.7 V (device driven by totem pole driver)
Symbol
Parameter
VCC =2.7 - 3.6 V
VCC =4.3 - 5.5V
Unit
Min.
Max.
Min.
Max.
tRVCC
Rise time I/OVCC
6.9
4.0
ns
tFVCC
Fall time I/OVCC
14.8
19.1
ns
tRVL
Rise time I/OVL
5.3
5.6
ns
tFVL
Fall time I/OVL
9.8
10.0
ns
tI/OVL-VCC
Propagation delay time
I/OVCC-LH to I/OVL-LH
I/OVCC-HL to I/OVL-HL
tPLH
3.2
3.1
ns
tPHL
8.2
11.6
ns
tI/OVCC-VL
Propagation delay time
I/OVCC-LH to I/OVL-LH
I/OVCC-HL to I/OVL-HL
tPLH
2.6
2.2
ns
tPHL
5.3
5.9
ns
tPZL
tPLZ
Output enable and
disable time
En
8
12
ns
Dis
40
40
ns
DR
Data rate(1)
9
6.8
MHz
1. The data rate is guaranteed based on the condition that the output I/O signal rise/fall time is less than 15% of
the input I/O signal period; the input I/O signal is at 50% duty cycle and the output I/O signal duty cycle
deviation not less than 30%.
Table 12. AC characteristics - test conditions: VL = 2.7 - 3.6 V (device driven by totem pole driver)
Symbol
Parameter
VCC =4.3 - 5.5V
Unit
Min.
Max.
tRVCC
Rise time I/OVCC
4.3
ns
tFVCC
Fall time I/OVCC
17.2
ns
tRVL
Rise time I/OVL
4.5
ns
tFVL
Fall time I/OVL
9.7
ns
tI/OVL-VCC
Propagation delay time
I/OVL-LH to I/OVCC-LH
I/OVL-HL to I/OVCC-HL
tPLH
2.7
ns
tPHL
10.6
ns
tI/OVCC-VL
Propagation delay time
I/OVCC-LH to I/OVL-LH
I/OVCC-HL to I/OVL-HL
tPLH
1.9
ns
tPHL
4.8
ns
tPZL
tPLZ
Output enable and disable time
En
7ns
Dis
40
ns
DR
Data rate(1)
7.2
MHz
1. The data rate is guaranteed based on the condition that the output I/O signal rise/fall time is less than 15% of
the input I/O signal period; the input I/O signal is at 50% duty cycle and the output I/O signal duty cycle
deviation not less than 30%.



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