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DP8403 Fiches technique(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce DP8403
Description  DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDACs)
PDF  18 Pages
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8403 Fiches technique(HTML) 10 Page - National Semiconductor (TI)

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Absolute Maximum Ratings
If MilitaryAerospace specified devices are required
please contact the National Semiconductor Sales
OfficeDistributors for availability and specifications
Over Operating Free-Air Temperature Range (unless otherwise noted)
Supply Voltage VCC (See Note 1)
7V
Input Voltage CB and DB
55V
All Others
7V
Operating Free-Air Temperature Military b55 Cto a125 C
Commercial
0 to a70 C
Storage Temperature Range
b
65 Cto a150 C
Recommended Operating Conditions
Symbol
Parameter
Conditions
Military
Commercial
Units
Min
Typ
Max
Min Typ
Max
VCC
Supply Voltage
45
5
55
45
5
55
V
VIH
High-Level Input Voltage
2
2
V
VIL
Low-Level Input Voltage
08
08
V
IOH
High-Level Output Current
ERR Or MERR
b
04
b
04
mA
DB Or CB
DP8402A DP8404
b
1
b
26
IOL
Low-Level Output Current
ERR Or MERR
48
mA
DB or CB
12
24
tw
Pulse Duration
LEDBO Low
25
25
ns
(1) Data And Check Word Before S0
u
15
10
(S1 e H)
(2) SO High Before LEDBO
u (S1 e H)
45
45
(3) LEDBO High Before The Earlier
00
of S0
v or S1v
tsu
Setup Time
(4) LEDBO High Before S1
u (S0 e H)
0
0
ns
(5) Diagnostic Data Word Before S1
u
15
10
(S0 e H)
(6) Diagnostic Check Word Before
15
10
The Later Of S1
v or S0u
(7) Diagnostic Data Word Before
25
20
LEDBO
u (S1 e L and S0 e H)
(8) Read-Mode S0 Low And S1 High
35
30
(9) Data And Check Word After
20
15
S0
u (S1 e H)
th
Hold Time
(10) Data Word After S1
u (S0 e H)
20
15
ns
(11) Check Word After The Later
20
15
of S1
v or S0u
(12) Diagnostic Data Word After
00
LEDBO
u (S1 e L And S0 e H)
tcorr
Correction Time (see
Figure 1 )
65
58
ns
TA
Operating Free-Air Temperature
b
55
125
0
70
C
This specification may be interpreted as the maximum delay to guarantee valid corrected data at the output and includes the tsu setup delay
These times ensure that corrected data is saved in the output data latch
These times ensure that the diagnostic data word is saved in the output data latch
10



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