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STM32F410RB Fiches technique(PDF) 105 Page - STMicroelectronics

No de pièce STM32F410RB
Description  Clock, reset and supply management
PDF  142 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F410RB Fiches technique(HTML) 105 Page - STMicroelectronics

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STM32F410x8/B
Electrical characteristics
118
Figure 32. SPI timing diagram - slave mode and CPHA = 0
ta(SO)
Data output access time Slave mode
7
-
21
ns
tdis(SO)
Data output disable time Slave mode
5
-
12
ns
tv(SO)
Data output valid time
Slave mode (after enable edge),
2.7 V < VDD < 3.6 V
-11
13
ns
Slave mode (after enable edge),
1.7 V < VDD < 3.6 V
-
11
18.5
ns
th(SO)
Data output hold time
Slave mode (after enable edge),
1.7 V < VDD < 3.6 V
8-
-
ns
tv(MO)
Data output valid time
Master mode (after enable edge)
-
4
6
ns
th(MO)
Data output hold time
Master mode (after enable edge)
0
-
-
ns
1. Guaranteed by characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
Table 64. SPI dynamic characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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