ST72561J4-Auto datasheet(84/324 Pages) STMICROELECTRONICS

No de pièce	ST72561J4-Auto

Description	Clock, reset and supply management

PDF	324 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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84 / 324 page

Window watchdog (WWDG)

ST72561-Auto

84/324

Doc ID 12370 Rev 8

9.4

Using halt mode with the WDG

If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT

instruction), it is recommended before executing the HALT instruction to refresh the WDG

counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

9.5

How to program the watchdog timeout

Figure 35 shows the linear relationship between the 6-bit value to be loaded in the

Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be

used for a quick calculation without taking the timing variations into account. If more

precision is needed, use the formulae in Figure 36.

Caution:

When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 35.

Approximate timeout duration

Watchdog timeout (ms) @ 8 MHz fOSC2

128

1.5

114

ST72561J4-Auto Fiches technique(PDF) 84 Page - STMicroelectronics