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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST72361AR4-Auto Fiches technique(PDF) 56 Page - STMicroelectronics |
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ST72361AR4-Auto Fiches technique(HTML) 56 Page - STMicroelectronics |
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56 / 279 page  Interrupts ST72361xx-Auto 56/279 Doc ID 12468 Rev 3 6.6 External interrupts 6.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the ISxx bits in the EICR register (Figure 21). This control allows up to four fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: ● Falling edge ● Rising edge ● Falling and rising edge ● Falling edge and low level To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a different value in the ISx[1:0] of the EICR. |
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