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ST72325AR7-Auto Fiches technique(PDF) 216 Page - STMicroelectronics |
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ST72325AR7-Auto Fiches technique(HTML) 216 Page - STMicroelectronics |
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216 / 243 page ![]() Obsolete Product(s) - Obsolete Product(s) Electrical characteristics ST72325xxx-Auto 216/243 Doc ID 13770 Rev 3 Figure 93. SPI master timing diagram(1) 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration. SS INPUT CPHA = 0 MOSI OUTPUT MISO INPUT CPHA = 0 CPHA = 1 CPHA = 1 tc(SCK) tw(SCKH) tw(SCKL) th(MI) tsu(MI) MSB IN MSB OUT BIT6 IN BIT6 OUT LSB OUT LSB IN See note 2 See note 2 CPOL = 0 CPOL = 1 CPOL = 0 CPOL = 1 tr(SCK) tf(SCK) th(MO) tv(MO) |
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