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ST72325AR7-Auto Fiches technique(PDF) 215 Page - STMicroelectronics

No de pièce ST72325AR7-Auto
Description  SCI asynchronous serial interface
PDF  243 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72325AR7-Auto Fiches technique(HTML) 215 Page - STMicroelectronics

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Product(s)
ST72325xxx-Auto
Electrical characteristics
Doc ID 13770 Rev 3
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Figure 91.
SPI slave timing diagram with CPHA = 0(1)
1.
Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends on the I/O port configuration.
Figure 92.
SPI slave timing diagram with CPHA = 1(1)
1.
Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
SS INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tv(SO)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
See note 2
CPOL=0
CPOL=1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
See
note 2
BIT1 IN
SS INPUT
CPHA=1
MOSI INPUT
MISO OUTPUT
CPHA=1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
BIT6 OUT
LSB OUT
See
CPOL=0
CPOL=1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
See
note 2
note 2
tc(SCK)
HZ
tv(SO)
MSB IN
LSB IN
BIT1 IN



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