ST7LITE49K2 datasheet(231/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

Device configuration and ordering information

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Bit 1 = WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

Bit 0 = WDG HALT Watchdog Reset on Halt

This option bit determines if a Reset is generated when entering Halt mode while the

Watchdog is active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

14.1.2

Option byte 0

OPT 7 = AWUCK Auto-wakeup clock selection

0: 32-kHz Oscillator (VLP) selected as AWU clock

1: AWU RC Oscillator selected as AWU clock.

Note:

If this bit is reset, OSCRANGE[2:0] must be set to 100.

OPT6:4 = OSCRANGE[2:0] Oscillator range

When the internal RC oscillator is not selected (CKSEL1=1), these option bits (and

CKSEL0) select the range of the resonator oscillator current source or the external

clock source.

OPT 3:2 = SEC[1:0] Sector 0 size definition

These option bits indicate the size of sector 0 according to Table 109.

Table 108.

Selection of the resonator oscillator range

OSCRANGE(1)

When the internal RC oscillator is selected, the CLKSEL option bits must be kept at their default value in

order to select the 256 clock cycle delay (see Section 7.3).

Typ. frequency range

with Resonator

1~2 MHz

2~4 MHz

4~8 MHz

8~16 MHz

VLP

32.768 kHz

External Clock on OSC1/CLKIN

Reserved

External Clock on PB1

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