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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST7DALIF2 Fiches technique(PDF) 43 Page - STMicroelectronics |
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ST7DALIF2 Fiches technique(HTML) 43 Page - STMicroelectronics |
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43 / 171 page  ST7DALIF2 Supply, reset and clock management 43/171 Figure 18. Using the AVD to monitor VDD 9.7.3 Low power modes Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction). VDD VIT+(AVD) VIT-(AVD) AVDF bit 01 RESET IF AVDIE bit = 1 Vhyst AVD INTERRUPT REQUEST INTERRUPT Cleared by VIT+(LVD) VIT-(LVD) LVD RESET Early warning interrupt (Power has dropped, MCU not not yet in reset) 0 1 hardware INTERRUPT Cleared by reset Table 12. Effect of low power modes on SI Mode Description Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode. Halt The SICSR register is frozen. The AVD remains active. Table 13. Interrupt control bits Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No |
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