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SPC560B64x Fiches technique(PDF) 79 Page - STMicroelectronics

No de pièce SPC560B64x
Description  Variable length encoding
PDF  133 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPC560B64x Fiches technique(HTML) 79 Page - STMicroelectronics

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DocID15131 Rev 9
79/133
SPC560B54x/6x
Electrical characteristics
132
4.8
Power management electrical characteristics
4.8.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the
common I/O supply VDD. The following supplies are involved:
HV: High voltage external power supply for voltage regulator module. This must be
provided externally through VDD power pin.
BV: High voltage external power supply for internal ballast module. This must be
provided externally through VDD_BV power pin. Voltage values should be aligned with
VDD.
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is
generated by the internal voltage regulator but provided outside to connect stability
capacitor. It is further split into four main domains to ensure noise isolation between
critical LV modules within the device:
LV_COR: Low voltage supply for the core. It is also used to provide supply for
FMPLL through double bonding.
LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double
bonding.
Figure 9. Voltage regulator capacitance connection
DEVICE
VSS_LV
VDD_BV
VDD_LV
VSS_LV
VDD_LV
VDD
VSS_LV
VDD_LV
CREG2 (LV_COR/LV_CFLA)
CREG3
CDEC2
DEVICE
VDD_BV
I
VDD_LVn
VREF
VDD
Voltage Regulator
VSS
VSS_LVn
(supply/IO decoupling)
(LV_COR/LV_PLL)



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