L6759D datasheet(36/51 Pages) STMICROELECTRONICS

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Efficiency optimization

L6759D

36/51

Doc ID 023240 Rev 1

In fact, high driving voltages are required to get good efficiencies in high loading conditions.

On the contrary, in lower loading conditions, such high driving voltage penalizes efficiency

because of high losses in Qgs. GDC allows to tune the MOSFET driving voltage according

to the delivered current.

Default configuration considers GDC always switched to VDRV except when the current

monitor is lower than N*10 or when entering power states higher than PS01h (included): in

this case, to further increase efficiency, simply supply the Phase1 and Phase2 driver

through the GDC pin. Their driving voltage is automatically updated as lower power states

are commanded through the SVI interface.

Further optimization may be possible by properly setting the automatic GDC threshold

through a dedicated PMBus command. It is then possible to modify the gate driving voltage

switch-over in PS00h. According to the positioning of the threshold compared with DPM

thresholds, it is possible to achieve different performances. Simulations and/or bench tests

may be of help in defining the best performing configuration achievable with the active and

passive components available.

Figure 13 gives a comparison of the efficiency improvements with DPM/GDC enabled with

respect to standard solutions.

Figure 13.

Efficiency performances with and without enhancements (DPM, GDC)

L6759D Fiches technique(PDF) 36 Page - STMicroelectronics