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ST1S41 Fiches technique(PDF) 16 Page - STMicroelectronics |
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ST1S41 Fiches technique(HTML) 16 Page - STMicroelectronics |
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16 / 27 page ![]() Application information ST1S41 16/27 DocID023654 Rev 2 Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order of 1% of VINMAX. In Table 6 some multi-layer ceramic capacitors suitable for this device are reported. A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1 uF. 6.2 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value to have the expected current ripple must be selected. The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current. In continuous current mode (CCM), the inductance value can be calculated by the following equation: Equation 19 where TON is the conduction time of the high-side switch and TOFF is the conduction time of the low-side switch (in CCM, FSW=1/(TON + TOFF)). The maximum current ripple, given the Vout, is obtained at maximum TOFF, that is at minimum duty cycle (see previous section to calculate minimum duty). So, fixing ΔIL=20% to 30% of the maximum output current, the minimum inductance value can be calculated as: Equation 20 where FSWMIN is the minimum switching frequency, according to Table 4. The peak current through the inductor is given by: Equation 21 Table 6. Input MLCC capacitors Manufacturer Series Cap value ( μF) Rated voltage (V) Murata GRM31 10 25 GRM55 10 25 TDK C3225 10 25 ΔI L V IN V OUT – L ------------------------------ T ON ⋅ V OUT L -------------- T OFF ⋅ == L MIN V OUT ΔI MAX ---------------- 1D MIN – F SWMIN ----------------------- ⋅ = I LPK , I O ΔI L 2 -------- + = |
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