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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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PC87332VLJ Fiches technique(PDF) 90 Page - National Semiconductor (TI) |
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PC87332VLJ Fiches technique(HTML) 90 Page - National Semiconductor (TI) |
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90 / 98 page  90 Electrical Characteristics (Continued) 936 Receiver Timing Symbol Parameter Conditions Min Max Units tRAI Delay from Active Edge of RD to Reset IRQ 78 ns tRINT Delay from Inactive Edge of RD (RD LSR) to Reset IRQ 55 ns tSCD Delay from RCLK to Sample Time (Note 1) 41 ns tSINT Delay from Stop Bit to Set Interrupt 2 Baud Out Cycles Note 1 This is an internal timing and is therefore not tested TLC11930 – 45 FIGURE 9-6a Sample Clock Timing TLC11930 – 29 FIGURE 9-6b Receiver Timing TLC11930 – 30 Note 2 If SCR0 e 1 then tSINT e 3 RCLKs For a Timeout interrupt tSINT e 8 RCLKs FIGURE 9-6c FIFO Mode Receiver Timing 90 |
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