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PC87311AVF Fiches technique(PDF) 67 Page - National Semiconductor (TI) |
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PC87311AVF Fiches technique(HTML) 67 Page - National Semiconductor (TI) |
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67 / 78 page ![]() 90 Device Description (Continued) 925 Transmitter Timing Symbol Parameter Min Max Units tHR Delay from WR (WR THR) to Reset IRQ 55 ns tIR Delay from RD (RD IIR) to Reset IRQ (THRE) 55 ns tIRS Delay from Initial IRQ Reset to Transmit Start 8 24 BAUDOUT Cycles tSI Delay from Initial Write to IRQ 16 24 BAUDOUT Cycles tSTI Delay from Start Bit to IRQ (THRE) 8 BAUDOUT Cycles TLF11362 – 21 Note 1 See Write cycle timing Figure 9-3 Note 2 See Read cycle timing Figure 9-2 FIGURE 9-5 Transmitter Timing 67 |
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