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L3GD20H Fiches technique(PDF) 43 Page - STMicroelectronics |
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L3GD20H Fiches technique(HTML) 43 Page - STMicroelectronics |
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43 / 52 page ![]() DocID023469 Rev 2 43/52 L3GD20H Register description 7.14 FIFO_SRC (2Fh) 7.15 IG_CFG (30h) Table 40. FIFO_CTRL register description FM2-FM0 FIFO mode selection. Default value: 000 (see Table 41) FTH4-FTH0 FIFO threshold setting. Default value: 0 Table 41. FIFO mode configuration FM2 FM1 FM0 FIFO mode 000Bypass mode 001FIFO mode 010Stream mode 011Stream-to-FIFO mode 100Bypass-to-stream mode 110Dynamic stream mode 111Bypass-to-FIFO mode Table 42. FIFO_SRC register FTH OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 Table 43. FIFO_SRC register description FTH FIFO threshold status. (0: FIFO filling is lower than FTH level; 1: FIFO filling is equal or higher than FTH level) OVRN Overrun bit status. (0: FIFO is not completely filled; 1:FIFO is completely filled) EMPTY FIFO empty bit. ( 0: FIFO not empty; 1: FIFO empty) FSS4-FSS0 FIFO stored data level of the unread samples Table 44. IG_CFG register AND/OR LIR ZHIE ZLIE YHIE YLIE XHIE XLIE |
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