AT89C51CC03U-RDTIM datasheet(92/195 Pages) ATMEL

92 / 195 page

AT89C51CC03

4182I–CAN–06/05

Figure 48. CAN Controller Memory Organization

Ch.14 - ID Tag - 1

Ch.14 - ID Tag - 2

Ch.14 - ID Tag - 4

Ch.14 - ID Tag - 3

Ch.14 - ID Mask - 1

Ch.14 - ID Mask - 2

Ch.14 - ID Mask - 4

Ch.14 - ID Mask - 3

Ch.14 - Message Data - byte 0

General Control

General Status

Bit Timing - 1

Bit Timing - 2

Bit Timing - 3

Enable Interrupt

Enable Interrupt message object - 1

Page message object

message object Status

message object Control and DLC

Message Data

ID Tag - 1

ID Tag - 2

ID Tag - 4

ID Tag - 3

ID Mask - 1

ID Mask - 2

ID Mask - 4

ID Mask - 3

message object 0 - Status

message object 0 - Control and DLC

Ch.0 - ID Tag - 1

Ch.0 - ID Tag - 2

Ch.0 - ID Tag - 4

Ch.0 - ID Tag - 3

Ch.0 - Message Data - byte 0

message object 14 - Status

message object 14 - Control and DLC

Enable Interrupt message object - 2

Status Interrupt message object - 1

Status Interrupt message object - 2

(message object number)

(Data offset)

SFR’s

On-chip CAN Controller registers

15 message objects

8 Bytes

TimStmp High

TimStmp Low

Ch.0 - ID Mask- 1

Ch.0 - ID Mask- 2

Ch.0 - ID Mask - 4

Ch.0 - ID Mask- 3

CANTimer High

CANTimer Low

TimTTC High

TimTTC Low

TEC counter

REC counter

Timer Control

Enable message object - 1

Enable message object - 2

message object Window SFRs

Ch.0 TimStmp High

Ch.0 TimStmp Low

Ch.14 TimStmp High

Ch.14 TimStmp Low

General Interrupt

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