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ADA2200ARUZ Fiches technique(PDF) 5 Page - Analog Devices

No de pièce ADA2200ARUZ
Description  Demodulates signal input bandwidths to 30 kHz
PDF  25 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADA2200ARUZ Fiches technique(HTML) 5 Page - Analog Devices

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ADA2200
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL I/O
Logic Thresholds
All inputs/outputs
Input Voltage
Low
0.8
V
High
2.0
V
Output Voltage
Low
While sinking 200 µA
0.4
V
High
While sourcing 200 µA
VDD − 0.4
V
Maximum Output Current
Sink or source
8
mA
Input Leakage
1
µA
Internal Pull-Up Resistance
BOOT and RST only
40
kΩ
CRYSTAL OSCILLATOR
Internal Feedback Resistor
500
kΩ
CLKIN Capacitance
2
pF
XOUT Capacitance
2
pF
POWER REQUIREMENTS
Power Supply Voltage Range
2.7
3.6
V
Total Supply Current Consumption
395
485
µA
1
See the Terminology section.
2
Common-mode signal swept from fMOD − 1 kHz to fMOD + 1 kHz. Output measured at frequency offset from fMOD. For example, a common-mode signal at fMOD − 500 Hz is
measured at 500 Hz.
3
The input impedance is equal to a 4 pF capacitor switched at fCLKIN. Therefore, the input impedance = 1012/(2πfCLKIN × 4).
SPI TIMING CHARACTERISTICS
VDD = 2.7 V to 3.6 V, default register configuration, TA = −40 to +85°C, unless otherwise noted.
Table 2. SPI Timing
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
fSCLK
50% ± 5% duty cycle
20
MHz
t
CS
CS to SCLK edge
2
ns
tSL
SCLK low pulse width
10
ns
tSH
SCLK high pulse width
10
ns
tDAV
Data output valid after SCLK edge
20
ns
tDSU
Data input setup time before SCLK edge
2
ns
tDHD
Data input hold time after SCLK edge
2
ns
tDF
Data output fall time
1
ns
tDR
Data output rise time
1
ns
tSR
SCLK rise time
10
ns
tSF
SCLK fall time
10
ns
tDOCS
Data output valid after CS edge
1
ns
tSFS
CS high after SCLK edge
2
ns
Rev. 0 | Page 4 of 24



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