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MB91F467DA Fiches technique(PDF) 103 Page - Cypress Semiconductor

No de pièce MB91F467DA
Description  32-bit RISC, load/store architecture, five-stage pipeline
PDF  137 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB91F467DA Fiches technique(HTML) 103 Page - Cypress Semiconductor

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Document Number: 002-04613 Rev. *A
Page 103 of 137
MB91460D Series
15.7.5 Free-run timer clock
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = 40°C to  105°C)
Note : tCLKP is the cycle time of the peripheral clock.
15.7.6 Trigger input timing
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = 40°C to  105°C)
Note : tCLKP is the cycle time of the peripheral clock.
Parameter
Symbol
Pin name
Condition
Value
Unit
Min
Max
Input pulse width
tTIWH
tTIWL
CKn
—
4tCLKP
—ns
Parameter
Symbol
Pin name
Condition
Value
Unit
Min
Max
Input capture input trigger
tINP
ICUn
—
5tCLKP
—ns
A/D converter trigger
tATGX
ATGX
—
5tCLKP
—ns
tTIWH
tTIWL
CKn
VIH
VIH
VIL
VIL
ICUn,
ATGX
tATGX, tINP



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