MB91F577CSPMC datasheet(136/163 Pages) CYPRESS

136 / 163 page

Document Number: 002-04725 Rev.*A

Page 136 of 163

MB91570 Series

Bit setting: ESCR: SCES = 0, ECCR: SCDE = 1

(TA: Recommended operating conditions, VCC5 = 5.0V±10%, VCCE = 5.0V±10%, VSS = AVSS = 0.0V)

Parameter

Symbol

Pin name

Conditions

Value

Unit

Remarks

Min

Max

Serial clock cycle time

tSCYC

SCK2,SCK3,

SCK4,SCK5,

SCK6,SCK7

–

5tCPP

–

Internal shift clock mode:

CL=80pF+1 • TTL

SCK

↑→

SOT delay time

tSHOVI

SCK2,SCK3,

SCK4,SCK5,

SCK6,SCK7,

SOT2,SOT3,

SOT4,SOT5,

SOT6,SOT7

-50

+50

Valid SIN

→

SCK

↓setup time

tIVSLI

SCK2,SCK3,SCK4,

SCK5,SCK6,SCK7,

SIN2,SIN3,

SIN4,SIN5,

SIN6,SIN7

tCPP+80

–

SCK

↓→

Valid SIN hold time

tSLIXI

–

SOT

→

SCK

↓ delay time

tSOVLI

SCK2,SCK3,

SCK4,SCK5,

SCK6,SCK7,

SOT2,SOT3,

SOT4,SOT5,

SOT6,SOT7

3tCPP-70

–

Notes:

• CL is the load capacitance applied to pins during testing.

• The maximum baud rate is limited by the internal operation clock used and other parameters.

Refer to Hardware Manual for details.

Internal shift clock mode

2.4V

0.8V

SINx

SOTx

SCKx

SCYC

SLIXI

IVSLI

0.8V

2.4V

0.8V

SHOVI

SOVLI

MB91F577CSPMC Fiches technique(PDF) 136 Page - Cypress Semiconductor

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