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PI6C2516

Phase-Locked Loop Clock Driver

with 16 Clock Outputs

5

PS8440C

07/24/01

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SwitchingCharacteristics

Notes:

1. These parameters are not production tested.

3. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

Notes:

1. Operating Clock Frequency indicates a range over which the PLL must be able to lock, but in which it is not

required to meet the other timing parameters (used for low-speed system debug).

2. Application Clock Frequency indicates a range over which the PLL must meet all of the timing parameters.

3. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be

obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications

for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable.

4. Frequency and loading condition should not exceed 0.85 watt power dissipation (package limitation). Please refer to Graph 1.

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Clock Frequency (MHz)

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Load = 22pF

Load = 10pF

100

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