PD2436 datasheet(7/14 Pages) OSRAM

7 / 14 page

PD243X, PD353X, PD443X

2006-01-23

DC Characteristics at 25°C

Parameter

Limits

Conditions

Min.

Typ.

Max.

Units

4.5

5.0

5.5

Volts

Nominal

CC (Blank)

—

2.5

3.5

CC=5.0 V, A2 = 1, all other inputs low.

CC 80 LEDs/unit (100% Bright)

PD243X

PD353X

PD443X

—

115

145

150

130

165

170

CC=5.0 V

—

0.8

Volts

CC=4.5 V to 5.5 V

2.0

—

Volts

CC=4.5 V to 5.5 V

IL (except D0 to D7)

(1)

—

100

µA

CC=4.5 V to 5.5 V, VIN =0.8 V

—

0.4

Volts

CC=4.5 V to 5.5 V

2.4

—

Volts

CC=4.5 V to 5.5 V

–8.9

—

CC=4.5 V, VOH=2.4 V

1.6

—

CC=4.5 V, VOL=0.4 V

Data I/O Bus Loading

—

100

—

Clock I/O Bus Loading

—

240

—

D0 to D7 have no pull-up resistors so current is negligible.

Pin Assignments and Definitions

Function

Definition

Function

Definition

Active low, will enable a processor to read all

registers in the display.

Write. Active low. If the device is selected, a

low on the write input loads the data into mem-

ory.

CLK I/O

If CLK SEL (pin 3) is low, then expect an exter-

nal clock source into this pin. If CLK SEL is

high, then this pin will be the master or source

into this pin. If CLK SEL is high, then this pin

will be the master or source for all other

devices which have CLK SEL low.

Data Bus bit 7 (MSB).

CLKSEL

CLOCK SELECT determines the action of pin

2. CLK I/O, see the section on Cascading for

an example.

Data Bus bit 6.

RST

Reset. Used to synchronize blinking. Will not

clear the display. The reset pulse should be

less than 1 ms

Data Bus bit 5.

CE1

Chip enable (active high).

Data Bus bit 4.

CE0

Chip enable (active low).

Data Bus bit 3.

Address input (MSB).

Data Bus bit 2.

Address input.

Data Bus bit 1.

Address input (LSB).

Data Bus bit 0 (LSB).

GND

Ground.

Positive power pin.

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