ST62T80B datasheet(72/78 Pages) STMICROELECTRONICS

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ST62T80B/E80B

6.6 TIMER CHARACTERISTICS

(TA = -40 to +85°C unless otherwise specified)

Note*: When available.

6.7 SPI CHARACTERISTICS

(TA = -40 to +85°C unless otherwise specified)

6.8 LCD ELECTRICAL CHARACTERISTICS

(TA = -40 to +85°C unless otherwise specified)

Notes:

1. The DC offset refers to all segment and common outputs. It is the difference between the measured voltage value and nominal value for

every voltage level.

2. An external resistor network is required when VLCD is lower then 4.5V.

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

fIN

Input Frequency on TIMER Pin*

MHz

Pulse Width at TIMER Pin*

VDD = 3.0V

VDD >4.5V

125

µs

fINT

----------

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

FCL

Clock Frequency

Applied on Scl

MHz

tSU

Set-up Time

Applied on Sin

Hold Time

Applied onSin

100

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

Vos

DC Offset Voltage

VLCD = Vdd, no load

VOH

COM High Level, Output Voltage

SEG High Level, Output Voltage

I=100µA, VLCD=5V

I=50µA, VLCD=5V

4.5

VOL

COM Low Level, Output Voltage

SEG Low Level, Output Voltage

I=100µA, VLCD=5V

I=50µA, VLCD=5V

0.5

VLCD

Display Voltage

See Note 2

VDD -0.2

1118

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