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LM4560 Fiches technique(PDF) 3 Page - National Semiconductor (TI) |
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LM4560 Fiches technique(HTML) 3 Page - National Semiconductor (TI) |
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3 / 54 page ![]() Table of Contents (Continued) 4.1.8 PCI Buffer/Sample Cache 4.1.9 CODEC Buffer/Sample FIFO 4.1.10 Legacy Channel Playback/Recording 4.2 Legacy Audio 4.2.1 SB Engine: 4.3 Serial Interface 4.3.1 AC-97 Interface 4.3.2 I2S Interface 4.3.3 S/PDIF 4.4 Power Management 4.4.1 Power Management For D0–D3 States 4.4.2 D0–D3 State Transition Table 5.0 Signals and Timing 5.1.2 Timing 5.1.2.1 Slave read/write timing 6.0 Device Configuration 6.1 Overview 6.2 Configuration and GPIO Registers 7.0 Device Specifications 7.1 Absolute Maximum Ratings 7.2 Capacitance 7.3 Electrical Characteristics 7.4.1 Timing Table 7.4.2 PCI Signals Physical Dimensions List of Figures Figure 1. 100-Pin TQFP Package Figure 2. LM4560 Block diagram Figure 3. Wave Engine Block Diagram www.national.com 3 |
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