LAN9250 datasheet(188/421 Pages) MICROCHIP

188 / 421 page

LAN9250

DS00001913A-page 188

 2015 Microchip Technology Inc.

Flow Control on Broadcast Frame (FCBRD)

When this bit is set, the Host MAC will assert back pressure when the AFC

level is reached and a broadcast frame is received. This field has no function

in full-duplex mode.

0: Flow Control on Broadcast Frame Disabled

1: Flow Control on Broadcast Frame Enabled

R/W

Flow Control on Address Decode (FCADD)

When this bit is set, the Host MAC will assert back pressure when the AFC

level is reached and a frame addressed to the Host MAC is received. This

field has no function in full-duplex mode.

0: Flow Control on Address Decode Disabled

1: Flow Control on Address Decode Enabled

R/W

Flow Control on Any Frame (FCANY)

When this bit is set, the Host MAC will assert back pressure, or transmit a

pause frame when the AFC level is reached and any frame is received. Set-

ting this bit enables full-duplex flow control when the Host MAC is operating

in full-duplex mode.

When this mode is enabled during half-duplex operation, the Flow Controller

does not decode the Host MAC address and will send a JAM upon receipt of

a valid preamble (i.e., immediately at the beginning of the next frame after the

RX Data FIFO level is reached).

When this mode is enabled during full-duplex operation, the Flow Controller

will immediately instruct the Host MAC to send a pause frame when the RX

Data FIFO level is reached. The MAC will queue the pause frame transmis-

sion for the next available window.

Setting this bit overrides bits [3:1] of this register.

R/W

Bits

Description

Type

Default

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