USB2504 datasheet(10/42 Pages) MICROCHIP

10 / 42 page

USB2504/USB2504A

DS000002250A-page 10

 2007 - 2016 Microchip Technology Inc.

TABLE 4-2:

SMBUS OR EEPROM INTERFACE BEHAVIOR

CFG_SEL2

CFG_SEL1

CFG_SEL0

SMBus or EEPROM Interface Behavior

Configured as an SMBus slave for external download of user-

defined descriptors. SMBus slave address is 0101100

Configured as an SMBus slave for external download of user-

defined descriptors. SMBus slave address is 0101101

Internal Default Configuration

Internal Default Configuration via strapping options.

2-wire (I2C) EEPROMS are supported,

TABLE 4-3:

MISCELLANEOUS PINS

Name

Symbol

Type

Function

Crystal

Input/External

Clock Input

XTAL1/

CLKIN

ICLKx

24MHz crystal or external clock input.

This pin connects to either one terminal of the crystal or to

an external 24MHz clock when a crystal is not used.

Crystal Output

XTAL2

OCLKx

24MHz Crystal

This is the other terminal of the crystal, or left unconnected

when an external clock source is used to drive

XTAL1/CLKIN. It must not be used to drive any external

circuitry other than the crystal circuit.

Clock Input

Enable

CLKIN_EN

Clock In Enable:

Low = XTAL1 and XTAL2 pins configured for use with

external crystal

High = XTAL1 pin configured as CLKIN, and must be

driven by an external CMOS clock.

RESET Input

RESET_N

This active low signal is used by the system to reset the

chip. The minimum active low pulse is 1us.

Self-Power /

Bus-Power

Detect

SELF_PWR

Detects availability of local self-power source.

Low = Self/local power source is NOT available (i.e., Hub

gets all power from Upstream USB VBus).

High = Self/local power source is available.

TEST Pins

TEST[1:0]

IPD

Used for testing the chip. User must treat as a no-connect

or connect to ground.

Analog Test

Internal 1.8V

voltage regulator

enable

ATEST/

REG_EN

AIO

This signal is used for testing the analog section of the

chip, and to enable or disable the internal 1.8v regulator.

This pin must be connected to VDDA33 to enable the

internal 1.8V regulator, or to VSS to disable the internal

regulator.

When the internal regulator is enabled, the 1.8V power

pins must be left unconnected, except for the required

bypass capacitors.When the PHY is in test mode, the

internal regulator is disabled and the ATEST pin functions

as a test pin.

TABLE 4-4:

POWER, GROUND, AND NO CONNECT

Name

Symbol

Type

Function

VDD1P8

VDD18

+1.8V core power.

If the internal regulator is enabled, then VDD18 pin 54

must have a 4.7

F (or greater) ±20% (ESR <0.1

capacitor to VSS

VDDAPLL3P3

VDDA33PLL

+3.3V Filtered analog power for the internal PLL

If the internal PLL 1.8V regulator is enabled, then this pin

acts as the regulator input

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