WM8738ED datasheet(8/15 Pages) WOLFSON

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WM8738

Production Data

PD Rev 4.3 November 2004

DIGITAL AUDIO INTERFACE TIMING

M CLK

MCLKH

MCLKY

MCLKL

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

TMCLKH

MCLK System clock pulse width low

TMCLKL

MCLK System clock cycle time

TMCLKY

BCLK

LRCLK

BCH

BCL

BCY

SDATO

LRS U

LRH

Figure 2 Digital Audio Data Timing

Test Conditions

AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

LRCLK set-up time to BCLK

rising edge

tLRSU

LRCLK hold time from

BCLK rising edge

tLRH

SDATO propagation delay

from BCLK falling edge

tDD

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